CMOS transistors generally include source and drain regions interconnected by a channel region, and at least one gate that regulates current flow through the channel region. Contacts to the source and drain regions are often made by forming a metal silicide on the base source drain material, then depositing a dielectric over the transistor, patterning contact trenches in the dielectric, and lastly forming metal source drain contacts in the contact trenches.
The contact resistance between the metal contacts and the source drain material is an important consideration, especially with devices have scaled dimensions. Namely, as the contact area becomes increasingly smaller, contact resistance becomes a greater concern. Dopant implantation can be used to reduce the contact resistance. Phosphorous is a common dopant for n-type transistors. However, with conventional processes, the amount of phosphorous that can be used is limited by its chemical solubility.
Accordingly, techniques for reducing resistivity in source and drain contacts would be desirable.